A phase locked loop (PLL) is a known circuit that, generally, acts as a feedback control loop which employs the phase difference between a time-varying input signal and a time-varying output signal to force the output signal to a frequency that is proportionate to that of the input signal. PLLs are employed in a variety of applications such as synchronous data communications, tone decoding, demodulation of signals, frequency multiplication and synthesis, and signal regeneration. In such applications the PLL output generally used by downstream circuitry to in some way track the PLL input. PLLs and some of their applications are discussed, for example, in, “The Art of Electronics”, Second Edition, Paul Horowitz and Winfield Hill, Cambridge University Press, 1989, pp. 641, 655 which is hereby incorporated by reference.
PLLs may be characterized, in part, by their capture range and by their lock range. Typically, a PLL will be able to “capture”, or lock onto, signals having a relatively narrow range of frequencies. Once the signal is captured though, the PLL will be able to track the input signal through a larger range of frequencies, commonly referred to as the PLL's lock range. Should the frequency of the PLL's input signal change, for any of a number of reasons, to a frequency that falls outside the PLL's lock range, the PLL will “lose lock” and no longer track the input signal. In response to the loss of lock, the PLL may produce an output signal of somewhat random frequency or, in the course of attempting to reacquire lock, the PLL may “thrash about” thereby producing an output signal of wildly varying frequency. Such wild variations in a PLL output signal's frequency could severely disrupt the operation of circuitry that relies upon the PLL for a stable frequency source.
A PLL that is capable of detecting an input signal's frequency excursion outside a predetermined frequency range, such as the PLL's lock range, would therefore be advantageous. Additionally, a PLL that is capable of steady operation during such frequency excursions and is capable of “re-qualifying” an input signal once the input signal has returned to an acceptable frequency range would be highly desirable.
PLLs are often employed within telecommunications systems to provide re-timed synchronization signals throughout a telecommunications system network. Such re-timed signals may be employed to distribute clock signals within a SONET network, for example. Such clocks are typically arranged in a hierarchy, with the clock's frequency accuracy determining the clock's hierarchical ranking. That is, a Stratum I clock, the most accurate, provides a frequency accuracy of 1×10−11 parts per million (PPM), a Stratum II clock provides a frequency accuracy of 1.6×10−8 PPM, and so on. Stratum clocks and SONET networks are known and are discussed, for example, in “SONET Transport Systems: Common Criteria Network Element Architectural Features”, Bellcore document GR-253-CORE, Issue 2, December 1995, “Clocks For The Synchronized Network: Common Generic Criteria”, Bellcore document GR-1244-CORE, Issue 1, June 1995, and “Generic Requirements For Timing Signal Generators”, Bellcore document GR-378-CORE, Issue 1, June 1995, all of which are hereby incorporated by reference.
Upper level Stratum clocks provide synchronization to lower level Stratum clocks. That is, a Stratum I clock may provide synchronization information to a Stratum II, Stratum III or lower level clock, but a Stratum II clock will not provide synchronization to a Stratum I clock. Should an upstream Stratum I clock fail, sending it's output signal to a frequency outside it's specified accuracy, for example, downstream clocks which are synchronized to the failed upstream clock may attempt, in the manner described above in relation to PLLs, to synchronize to the failed upstream clock. A PLL that is capable of detecting an input signal's frequency deviation, of providing a steady output signal during such an excursion, and of re-qualifying the signal from an upstream clock, would be particularly advantageous within a telecommunications system clock such as a SONET Stratum clock. Stratum clocks provide clock pulses that are relatively free of jitter and wander for use in telecommunications system. Stratum clocks are known and described, for example, in U.S. Pat. No. 5,596,614, which is hereby incorporated by reference.